FPGA/PLD
Integrated FPGA Design Flow
- Design Creation - Manage, create and analyze complex HDL designs
- Simulation - Simulate complex designs regardless of platform or language
- Synthesis - Advanced synthesis for complex FPGA and ASIC designs
Featured FPGA/PLD Techpubs
Demystifying DO-254
Interest in DO-254 first occurred in Europe and has since spread to the US commercial aircraft industry. If you are being asked about your company's DO-254 direction and compliance, but have been overwhelmed with information on the subject, then this article is for you. This article presents DO-254 for the novice, boiling down the standard, reducing it to its essential points so that you will be ready to respond with confidence, as well as understand its potential impact on your products or services.
Turning New Ideas into Reality using FPGAs and Structured ASICs
With their shorter development times, FPGAs and structured ASICs are a viable solution for shrinking market windows. This paper discusses a case study in which Infineon Technologies sought alternative solutions and elected to design with Altera Stratix FPGAs and HardCopy structured ASICs. It also discusses how Mentor Graphics EDA software can accelerate overall system design.
Ensuring Serial Protocol Signal Integrity with FPGAs and Embedded Transceivers
Transceivers have become commonplace in many applications across all markets. This drive, fuelled by the desire to move more data, is supplemented by the emergence of many new transmission protocols. Today’s FPGAs with embedded transceivers support many widely accepted serial protocol standards, including Gigabit Ethernet, PCI Express, XAUI and Serial Rapid IO. Maintaining signal integrity is a key element for the successful implementation of these standards within high bandwidth applications. This paper discusses the complex issues facing system designers, and FPGA-based solutions that support high-speed applications and protocols.
Technical Events:
- Optimize System Performance with FPGA/PCB Co-Design
- online
- Calibre Design-to-Silicon Platform Workshop
Jan 13, 2009 - San Jose, CA
- Incorporating SystemVerilog in a Productive FPGA Methodology Workshop
Jan 13, 2009 - San Jose, CA
News and Related Articles
- Mentor Graphics Announces Precision Synthesis Support for New Xilinx Virtex-5 TXT Field Programmable Gate Arrays Sep 23, 2008
- Thales and Mentor Graphics Halve Time-to-Productivity for New Design EngineersMay 27, 2008
- Mentor Graphics Supports Altera’s Stratix IV FPGA Device Family for 40 Nanometer Design ApplicationsMay 19, 2008